2026 DAC’26 RTL-3D: Timing-aware Tier Partitioning for 3D ICs Using Pre-synthesis Timing Analysis Haoyang Xu, Zheng Yang, Zhen Zhuang, and 4 more authors In ACM/IEEE The Chips to Systems Conference (DAC), Jul 2026 DAC’26 Mixed-structure Double-sided Redistribution Layer Routing for Glass Interposer-based 5.5D ICs Haoyang Xu, Zhen Zhuang, Leilei Jin, and 5 more authors In ACM/IEEE The Chips to Systems Conference (DAC), Jul 2026 DAC’26 BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs Leilei Jin, Haoyang Xu, Siyuan Liang, and 6 more authors In ACM/IEEE The Chips to Systems Conference (DAC), Jul 2026 2025 TCAD’25 Hierarchical Partitioning-Based Inter-Chip Redistribution Layer Routing for Fan-Out Wafer-Level Packaging Haoyang Xu, Xing Huang, Zhen Zhuang, and 6 more authors IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jul 2025 DOI
